The insulated-gate field-effect transistor (IGFET) has been arranged in various configurations of bistable stages, or cells, resembling bipolar transistor flip-flops. Unlike a conventional bipolar junction transistor, in which both majority and minority carriers are required for operation, an IGFET is a unipolar transistor to the extent that only majority carriers are required for operation. Conduction in an IGFET device is controlled by signals applied to a control electrode, without any current flow between the control electrode and controlled electrodes because the control electrode in insulated from the controlled electrodes. IGFET memory cells consume significantly less power than bipolar transistor cells.
In the background art, each IGFET memory cell generally requires at least four leads to the cell, a pair of cross-coupled inverter IGFET devices, a pair of load devices, and two additional gating IGFET devices for transferring information into and out of the cell.
A typical memory cell 100 as shown in FIG. 1 includes a pair of pull-up PMOS (p-channel metal-oxide-semiconductor) inverter transistors 101 and 102, and a pair of pull-down NMOS driver transistors 103 and 104. The gate electrodes of transistors 101 and 103 are cross-coupled to the gate electrodes of transistors 102 and 104. The transistors 101–104 comprise a data storage device, which serves to store bit values of “0” or “1.” The memory cell 100 further includes a pair of NMOS transfer transistors 105 and 106. Transistors 105 and 106 comprise data transfer devices, which serve to transfer information into and out of the memory cell 100.
Transfer transistor 105 is coupled to bit line BL and to node 1001 between the drain electrode of transistor 101 and the source electrode of transistor 103. Transfer transistor 106 is similarly coupled to complementary bit line/BL and to node 1002 between the drain electrode of transistor 102 and the source electrode of transistor 104. A gate electrode of each of transfer transistors 105 and 106 is coupled to word line WL. The transfer transistors 105 and 106 are thus made conductive by activating word line WL (i.e., by supplying a high voltage level to WL), which electrically connects bit line BL to node 1001 and complementary bit line/BL to node 1002.
The bit value of a memory cell is conventionally considered to be the value at node 1001, which is read out on bit line BL. When a bit value at node 1001 is “1” (V1001=Vcc) a bit value at node 1002 is “0” (V1002=0). Consequently, in this state, transistor 101 is turned on and transistor 103 is turned off by the voltage at node 1002, thereby keeping the voltage of node 1001 at Vcc. Similarly, the voltage Vcc at node 1001 turns off transistor 102 and turns on transistor 104, thereby coupling node 1002 to ground and keeping the voltage of node 1002 at V1002=0.
At the beginning of a read operation, bit lines BL and/BL are pre-charged to the supply voltage by a pre-charge signal. The word line WL is then enabled to turn on data transfer transistors 105 and 106 and thereby to connect bit-line BL to node 1001 and complementary bit-line/BL to node 1002. Because both bit line BL and node 1001 are at the supply voltage Vcc, the voltage on bit line BL remains substantially unchanged. However, because complementary bit line/BL is now coupled to ground through turned-on transistors 106 and 104, the pre-charge voltage at bit line/BL will be discharged to ground. As is well-known, sense amplifiers coupled to the bit lines BL and/BL sense the difference between the voltages on bit line BL and complementary bit line/BL to determine that memory cell 100 stores a bit value of “1.”
However, as the voltage on complementary bit-line/BL decreases below the supply voltage Vcc, the voltage at node 1002 will begin to rise above ground because transistors 104 and 106 will act as a voltage divider. Thus, there exists the possibility that the voltage at node 1002 may rise to a level that undesirably causes the memory cell 100 to switch its stored value from a “1” to a “0.”
As one conventional way to prevent this, the resistance of the transfer transistor 106 may be made higher than the resistance of driver transistor 104, such as by lengthening the channel of transistor 106. Conventionally, the IGFET devices have width-to-length ratios which are interrelated. The width w of each channel is the distance across the substrate surface of the semiconductor channel in a direction perpendicular to the direction of current in the channel. The length l of each channel is the distance between the source and drain electrodes in the direction of the current in the channel. The load devices have essentially equal width-to-length ratios w/l (L), and the gating devices also have essentially equal width-to-length ratios w/l (G). A relative ratio R relating the width-to-length ratios of the load and gating devices is given as:
  R  =                    w        /                  l          ⁡                      (            L            )                                      w        /                  l          ⁡                      (            G            )                                .  
If in a particular cell the ratio R is too small, stored information can be lost during a read operation because both cross-coupled inverter devices will be pulled into conduction rather than just one of them. This loss of information occurs because the voltage drop across one inverter transistor, which is correctly conducting, exceeds the threshold voltage of the opposite inverter transistor and causes it to also conduct but in error. On the other hand, if the ratio R is too large, bit-writing into the memory cell is made more difficult because very large voltage swings are required on the bit lines and on the word line for changing the state of the cell. This difficulty of changing the state of the cell occurs because the large ratio R involves devices which require more current through either inverter transistor to establish a source-to-drain voltage that exceeds the threshold voltage of the opposite inverter transistor.
Consequently, there is a trade-off balance that must be reached between providing a highly stable memory cell in which data is reliably stored without the possibility of loss of information, and providing a memory cell that has a fast read operation.
In the background art, in order to provide a stability index of a memory cell, the Static Noise Margin or SNM has been used. SNM is typically measured or simulated at the DC or quiescent state.
In particular, the stability of a memory cell may be described in terms of three stability modes: a storage mode; an active mode; and a transition mode. A memory cell is operating in the storage mode when it is not being accessed during a read or a write cycle. A memory cell is operating in the active mode when it is being accessed during a read or a write cycle. A cell is operating in the transition mode when it is transitioning between the active mode and the storage mode.
There are typical static noise margins associated with each of these operating modes that are used to determine the stability of the memory cell. When the memory cell is in the storage mode, the voltage on word line WL is a logic low, so that data transfer transistors 105 and 106 are substantially non-conductive, which isolates storage nodes 1001 and 1002 from the influence of the bit lines BL and/BL. The SNM during the storage mode varies, depending on the power supply voltage and the threshold voltage (Vth) variation between pull down transistors 103 and 104.
When the memory cell is in the active mode, the voltage of word line WL is a logic high, causing data transfer transistors 105 and 106 to be conductive. Storage nodes 1001 and 1002 are coupled to bit lines BL and/BL, respectively, and the memory cell 10 will be undergoing either a read operation or a write operation. During the active mode, the SNM varies according to the power supply voltage; the conductance ratio of transfer transistor 105 with respect to pull down transistor 103 (with a maximum gate voltage of pull down transistor 103 being set by the threshold voltage Vth of transfer transistor 105); the conductance ratio of transfer transistor 106 with respect to pull down transistor 104 (with the maximum gate voltage of pull down transistor 104 being set by the threshold voltage Vth of coupling transistor 106); and the amount of mismatch if any between the threshold voltages Vth and the conductance of pull down transistors 103 and 104.
When the memory cell is transitioning between the storage mode and the active mode, the voltage of word line WL is greater than ground, but less than supply voltage Vcc. As the word line voltage increases, the SNM associated with the storage mode degrades. As the word line voltage continues to increase, the storage mode SNM starts to become negative. As the storage mode SNM becomes negative, the active mode SNM should become positive to prevent the memory cell from becoming unstable and improperly changing logic states. Typically, the storage mode SNM should remain positive with word line voltages less than a few volts below the supply voltage, assuming a supply voltage Vcc that is approximately equal to 5 volts.
Using the SNM as an index indicates that stability of the memory cell is increased as the drivability of the data transfer transistors is reduced, e.g., by lengthening the channel in order to reduce the w/l ratio of the data transfer transistors with respect to the pull-down transistors. This result would appear to be reasonable since any noise or disturbance to the memory cell would be transmitted by the data transfer transistors.
However, reducing the drivability of the transfer gate transistors causes an increase of the word line load, and a decrease of memory cell current. Consequently, reduction in transfer gate drivability results in a longer read operation of the memory cell.
There, thus, exists a need in the art for, among other things, improvements to semiconductor memory cells to eliminate the shortcomings mentioned above.